The present invention relates to the fabrication of semiconductor devices. More particularly, the present invention relates to the fabrication of a guard cell that advantageously separates and protects one structure of the semiconductor device from other neighboring structures.
As is known in the art, various processes are used in the fabrication of semiconductor devices. Some of these processes, by the nature of the methods used, can have unintentional/undesired affects outside the specific area of fabrication. For example, several fabrication processes use an isotropic etch process. As is known in the art, an isotropic etch process removes material in all directions. Further, it may be difficult to control the depth of the etch performed by such isotropic etch processes. Thus, the etch may extend in a direction or to a depth beyond that needed or useful for the formation of the device to which the isotropic etch is directed.
An example of such a process is found in the fabrication of microcavities. Microcavities and their fabrication are known in the art. They are formed in conjunction with semiconductor devices such as electrically blowable fuses. In a typical electrically blowable fuse, the fuse portion is typically formed of a material that changes its state from conductive to non-conductive when a current exceeding a predefined threshold is passed through. This change in state sometimes produces particulate material. Accordingly, the fuse portion is typically disposed in a dielectric microcavity, i.e., a sealed, hollow chamber in a dielectric layer. Thus, any particulate material that may be formed when fuse portion is blown is kept contained with microcavity, thereby minimizing or essentially eliminating any possibility of particulate contamination of the IC surface. The microcavity itself is typically formed in a multi-step process.
To facilitate discussion, FIGS. 1A through 1C illustrate a prior art process for forming a microcavity in the context of an electrically blown fuse. Referring initially to FIG. 1A, a fuse portion 102 is shown disposed on a substrate 104. Fuse portion 102 typically comprises a conductor made of a suitable fuse material such as doped polysilicon or metal. The fuse portion is also sometimes capped with a silicon nitride layer 103. Above fuse portion 102, another oxide layer 106 is deposited. A silicon nitride layer 108 is then deposited above oxide layer 106.
Above silicon nitride layer 108, a photoresist layer 110 is deposited and patterned to form an opening 112. Patterned photoresist mask 110 is then employed to etch through silicon nitride layer 108 to expose a portion of oxide layer 106 above fuse portion 102. Although a patterned photoresist mask is shown here, other methods can be used to etch through silicon nitride layer 108 and expose a portion of the oxide layer 106. After an opening in silicon nitride layer 108 is formed, a subsequent isotropic etch is performed to create the microcavity. The microcavity etch preferably employs an etch process that is selective both to the liner material of fuse portion 102 and silicon nitride layer 108. As is apparent, with such a process silicon nitride layer 108 acts as a hard mask during the isotropic etch.
In FIG. 1B, microcavity 114 has been isotropically etched out of oxide layer 106 through the opening in silicon nitride layer 108. Subsequent to the formation of microcavity 114, the opening in silicon nitride layer 108 is sealed with plug material 116 while microcavity 114 is left hollow, thereby sealing fuse portion 102 within microcavity 114.
Due to the isotropic nature of the process, the degree to which the etch extends into oxide layer 106 is difficult to control. Thus, without taking steps to ensure otherwise, structures 118 which neighbor the fuse may be affected by the etch, as depicted in FIG. 1C, possibly resulting in the neighboring structures being damaged or made inoperative. To avoid such damage, the process may include accurately timing and halting the etch duration. This requires close monitoring of the etch process and is subject to error. Also, neighboring structures typically are located a distance from the fuse determined to be sufficient to avoid affecting those structures with the etch. Such distances may be determined from, among other factors, the characteristic interactions of the etch process and material being etched, such as the etch rate. Spacings used must be large enough to take into account the unpredictability of the process and possible errors in efforts to control the process. The requirement of such conservative spacings effectively limit the density with which devices can be formed on the IC, thereby limiting the number of devices that can be included on the IC.
In view of the foregoing, there are desired improved methods for forming microcavities in integrated circuits, which advantageously reduce required distances between semiconductor devices within the microcavity and neighboring devices, facilitating higher density IC's.